1. Technical Field
This invention relates to the semiconductor device fabrication, and more particularly to the testing of integrated circuits.
2. Background of the Technical Art
Final fabrication steps for an integrated circuit (IC) chip often include (1) the alignment and attachment of the IC chip leads to leads of a test device, and (2) the visual scanning of the IC chip leads for defects, such as misalignment.
Conventional chip aligners are used, for example, in test equipment to electrically test the leads of a chip. Mechanical adjustment of the chip lead positions and/or of the chip tester electrical contact positions is performed to correctly align the chip leads and the test leads. These adjustments may be required when a chip is initially placed in a testing area or when different types of chips with different lead configurations are tested in the same testing area.
Alignment is typically accomplished using precision-made machined components and making mechanical adjustments to these components to place the IC chip in the correct, aligned position. The problem with this method is that the machined parts wear out quickly due to the constant adjustments required to align chip leads with test leads. Since the machined parts must be very accurate in their dimensions, the cost in replacing the worn out parts can be high.
A further problem encountered in the prior art is that IC chip leads are now being manufactured with very small lead pitches. These pitches are often smaller than the tolerances of the machined parts, causing errors in aligning and testing the chip leads.
A still further problem in the prior art alignment apparatus is that the chip often slips or alters its position slightly before or during the testing process. The prior art does not address this problem of chip slippage or how to correct the alignment of the chip leads with the test leads once the slippage has occurred.
A visual inspection of the IC chip leads is often performed before or after aligning and electrically testing the leads. The scan is typically done optically, with an operator or computer visually checking for defects in the leads of the chip in a stand-alone apparatus. A problem with this prior art method is that separate machines are required to accomplish the scanning step and the alignment/testing step. Performance of separate tests for the alignment and scan requires additional time in order to move into place and apply the appropriate testing equipment, thus increasing the cost of testing the ICs. Furthermore, the IC leads can be bent out of alignment as they are being moved from the inspection apparatus to the testing apparatus.
What is needed is an approach that allows IC lead alignment and scanning to be accomplished with one apparatus that can be used for multiple purposes. Using one apparatus for both tasks allows more IC's to be tested and reduces damage to the ICs due to excessive handling.
What is further needed is an alignment apparatus that aligns an IC or other device under test after possible slippage of the IC on its testing platform. The apparatus should further provide accurate alignment of the IC leads and the test leads without the use of expensive, precision machined parts that wear out from constant adjustment.